Invention Grant
- Patent Title: Field effect transistor with reduced shallow trench isolation induced leakage current
- Patent Title (中): 场效应晶体管减少浅沟槽隔离引起的漏电流
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Application No.: US12041967Application Date: 2008-03-04
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Publication No.: US07804140B2Publication Date: 2010-09-28
- Inventor: Leland Chang , Anthony I. Chou , Shreesh Narasimha , Jeffrey W. Sleight
- Applicant: Leland Chang , Anthony I. Chou , Shreesh Narasimha , Jeffrey W. Sleight
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent H. Daniel Schnumann
- Main IPC: H01L27/088
- IPC: H01L27/088

Abstract:
Edges of source and drain regions along the direction of a channel of a field effect transistor are formed within an active area offset from the boundary between the active area and a shallow trench isolation structure. Such a structure may be manufactured by forming a gate electrode structure that overlies the boundary so that edges of the source and drain regions are self aligned to the edges of the gate electrode structure on the active area side of the boundary. Unnecessary portions of the gate electrode that does not overlie the source and drain regions may be removed to reduce parasitic capacitance. Shallow trench isolation edge current is eliminated since the semiconductor regions in the current path of the field effect transistor are offset from the boundary between the active area and the shallow trench isolation structure.
Public/Granted literature
- US20090224335A1 FIELD EFFECT TRANSISTOR WITH REDUCED SHALLOW TRENCH ISOLATION INDUCED LEAKAGE CURRENT Public/Granted day:2009-09-10
Information query
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