An efficient piezoelectric-triggered time delay module may be provided with separate firing and logic capacitors, and may also have corresponding separate piezoelectric transducers. Further, separate firing and logic capacitors may be impedance-matched to corresponding separate piezoelectric transducers. Optionally, the capacitors may be made of the same materials as the corresponding piezoelectric transducers. Further alternately or additionally, low-value, high-voltage rated capacitor(s) may be employed. Further alternately or additionally, the piezoelectric transducer(s) may be selected to offer high charge output within the intended operating temperature range. Further alternately or additionally, the piezoelectric transducer(s) may be constructed with multiple wafers.