A track-and-hold or sample-and-hold (S/H) circuit for an analog-to-digital converter (ADC) is provided. A difference between the disclosed S/H circuit and conventional S/H circuits is the use of a peaking circuit. This peaking circuit generally provides increased current to switching transistor when transitioning between track and hold which can increase the Spurious-Free Dynamic Range (SFDR) as low frequencies, by as much as 15dB.