One embodiment relates to an integrated circuit that includes a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric capacitor having a first plate and a second plate. The first plate is associated with a storage node of the ferroelectric memory cell, and the second plate associated with a plateline. The ferroelectric memory cell also includes a complementary transmission gate configured to selectively couple the storage node to a bitline as a function of a wordline voltage and a complementary wordline voltage. Bias limiting circuitry selectively alters voltage on the storage node as a function of the wordline voltage or the complementary wordline voltage. Other methods, devices, and systems are also disclosed.