A method for erasing a plurality of two-bit memory cells, each two-bit memory cell comprises a first bit and a second bit. A reference voltage is applied to a first bit line and a second bit line, the first bit line being associated with the first bits of each two-bit memory cell and the second bit line associated with the second bits of each two-bit memory cell. Then a control activation voltage is applied to a first bit line select and a second bit line select, each bit line associated with the first bits and the second bits of each memory cell, respectively. Then an operating voltage is applied to a plurality of word lines associated with each two-bit memory cell, wherein the operating voltage is between 14 and 20 volts.