Invention Grant
- Patent Title: System and method for memory phase shedding
- Patent Title (中): 内存相位脱落的系统和方法
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Application No.: US11968142Application Date: 2007-12-31
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Publication No.: US07804733B2Publication Date: 2010-09-28
- Inventor: James W. Alexander , Edward R. Stanford , Devadatta V. Bodas , Howard David , Son H. Lam
- Applicant: James W. Alexander , Edward R. Stanford , Devadatta V. Bodas , Howard David , Son H. Lam
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Grossman, Tucker, Perreault & Pfleger, PLLC
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
Embodiments of the invention supply power to DRAM or other memory devices with a multi-phase voltage regulator. A power controller coupled to the multi-phase voltage regulator causes one or more phases of the multi-phase voltage regulator to be activated or deactivated (shed) according to predetermined criteria. Embodiments of the invention thus improve power management by providing one or more reduced power states for the memory devices. Other embodiments are described.
Public/Granted literature
- US20090172442A1 SYSTEM AND METHOD FOR MEMORY PHASE SHEDDING Public/Granted day:2009-07-02
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