- Patent Title: Parallel data link layer controllers in a network switching device
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Application No.: US10751099Application Date: 2003-12-31
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Publication No.: US07805535B2Publication Date: 2010-09-28
- Inventor: Anees Narsinh , John Bailey
- Applicant: Anees Narsinh , John Bailey
- Applicant Address: FR Paris
- Assignee: Alcatel Lucent
- Current Assignee: Alcatel Lucent
- Current Assignee Address: FR Paris
- Agency: Galasso & Associates, LP
- Main IPC: G06F15/16
- IPC: G06F15/16

Abstract:
The present invention features a data link layer processor for performing VLAN tagging operations, policing, shaping, and statistics acquisition integrally with one or more media access controllers (MACs). When a plurality of data link layer processors are operated in parallel in a switching device, the computational burden carried by the route engine is significantly reduced. Moreover, the data link layer processor in its several embodiments may be used to introduce various forms of pre-processing and post-processing into network switching systems that employ route engines that do not posses such functionality.
Public/Granted literature
- US20050201415A1 Parallel data link layer controllers in a network switching device Public/Granted day:2005-09-15
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