Invention Grant
US07805590B2 Coprocessor receiving target address to process a function and to send data transfer instructions to main processor for execution to preserve cache coherence
有权
协处理器接收目标地址来处理一个功能，并将数据传输指令发送到主处理器进行执行以保持高速缓存一致性
- Patent Title: Coprocessor receiving target address to process a function and to send data transfer instructions to main processor for execution to preserve cache coherence
- Patent Title (中): 协处理器接收目标地址来处理一个功能，并将数据传输指令发送到主处理器进行执行以保持高速缓存一致性
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Application No.: US11426633Application Date: 2006-06-27
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Publication No.: US07805590B2Publication Date: 2010-09-28
- Inventor: William C. Moyer , Kevin B. Traylor
- Applicant: William C. Moyer , Kevin B. Traylor
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Daniel D. Hill; Joanna G. Chiu
- Main IPC: G06F9/312
- IPC: G06F9/312
Abstract:
A coprocessor (14) may be used to perform one or more specialized operations that can be off-loaded from a primary or general purpose processor (12). It is important to allow efficient communication and interfacing between the processor (12) and the coprocessor (14). In one embodiment, a coprocessor (14) generates and provides instructions (200, 220) to an instruction pipe (20) in the processor (12). Because the coprocessor (14) generated instructions are part of the standard instruction set of the processor (12), cache (70) coherency is easy to maintain. Also, circuitry (102) in coprocessor (14) may perform an operation on data while circuitry (106) in coprocessor (14) is concurrently generating processor instructions (200, 220).
Public/Granted literature
- US20070300044A1 METHOD AND APPARATUS FOR INTERFACING A PROCESSOR AND COPROCESSOR Public/Granted day:2007-12-27
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