In a multi-processor system (100), when a first processor interrupt generation unit (24) has executed a call command or a jump command in a main routine being executed, it generates an interrupt to a second processor. Upon reception of the interrupt from the interrupt generation unit (24), the second processor saves the return address for returning to the main routing upon completion of the subroutine processing called by the call command in a main memory area (54) other than the first processor or generates a call destination address and a jump destination address and reports it to the first processor. Thus, the first processor can be a small-size circuit capable of flexibly performing processing.