Invention Grant
- Patent Title: Circuit technique to reduce leakage during reduced power mode
- Patent Title (中): 降低功耗模式下减少泄漏的电路技术
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Application No.: US11394564Application Date: 2006-03-31
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Publication No.: US07805619B2Publication Date: 2010-09-28
- Inventor: John R. Cherukuri , Ak R. Ahmed , Arun Subbiah , Satish Damaraju
- Applicant: John R. Cherukuri , Ak R. Ahmed , Arun Subbiah , Satish Damaraju
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Erik R. Nordstrom
- Main IPC: G06F1/32
- IPC: G06F1/32
Abstract:
Provided herein are schemes for reducing leakage in dynamic circuits during sleep modes.
Public/Granted literature
- US20070236256A1 Circuit technique to reduce leakage during reduced power mode Public/Granted day:2007-10-11
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