Invention Grant
US07805627B2 Clock synchronization scheme for deskewing operations in a data interface
有权
时钟同步方案,用于数据接口中的歪斜操作
- Patent Title: Clock synchronization scheme for deskewing operations in a data interface
- Patent Title (中): 时钟同步方案,用于数据接口中的歪斜操作
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Application No.: US11729627Application Date: 2007-03-29
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Publication No.: US07805627B2Publication Date: 2010-09-28
- Inventor: Mamun Ur Rashid , Hing Y. To
- Applicant: Mamun Ur Rashid , Hing Y. To
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F1/04
- IPC: G06F1/04 ; G06F1/12 ; G06F1/14

Abstract:
A technique includes providing transmitters that are each associated with a data bit line of a bus, and each transmitter is clocked by an associated transmit clock signal. The technique includes determining a baseline offset to apply to a base clock signal to synchronize the base clock signal to a source clock signal of a source that supplies data to the transmitters. For each transmitter, an associated phase offset is determined to compensate for an associated skew. The phase of each transmit clock signal is controlled based on the associated phase offset and the baseline offset.
Public/Granted literature
- US20080244298A1 Clock synchronization scheme for deskewing operations in a data interface Public/Granted day:2008-10-02
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