A data processor includes a memory device having an array of memory cells for storing data values. Test circuitry executes one or more test patterns to detect any memory cells which may malfunction. Each test pattern causes a sequence of access requests to be issued to the memory device where the timing of the sequence is controlled by a test mode clock signal. Dummy read control circuitry is responsive at least to each write access request to generate an internal clock signal which has an increased frequency with respect to the test mode clock signal. The dummy read control circuitry performs, using the internal clock signal, a write operation to at least one memory cell based on a memory address specified by the write access request, followed by a dummy read operation to the same memory cell, serving to stress the memory cell with respect to cell stability.