A system for, and method of, testing a plurality of circuits, which may be unsingulated die on a wafer. In one embodiment, the system includes: (1) a test data interconnect that connects a test data output of a first circuit directly to a test data input of a second circuit located adjacent to the first circuit, (2) a test clock interconnect that connects a test clock output of the first circuit directly to a test clock input of the second circuit, (3) a test mode select interconnect that connects a test mode select output of the first circuit directly to a test mode select input of the second circuit and (4) a contact region coupled to provide test data, a test clock signal and a test mode select signal respectively to the test data interconnect, the test clock interconnect and the test mode select interconnect.