Invention Grant
- Patent Title: Memory construction apparatus for forming logical memory space
- Patent Title (中): 用于形成逻辑存储空间的存储器构造装置
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Application No.: US11698856Application Date: 2007-01-29
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Publication No.: US07805688B2Publication Date: 2010-09-28
- Inventor: Noritoshi Yamakawa , Hiroaki Miyamoto , Yoshikatsu Kouhara , Akitsugu Nakayama , Kouichi Tanda
- Applicant: Noritoshi Yamakawa , Hiroaki Miyamoto , Yoshikatsu Kouhara , Akitsugu Nakayama , Kouichi Tanda
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Staas & Halsey LLP
- Priority: JP2006-026256 20060202
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A logical memory construction-processing section reads several kinds of physical memories and registers prepared in advance as libraries, generates candidates for each logical memory, by combining only the physical memories or only the registers, or both the physical memories and the registers, with each other, so as to construct the logical memory that satisfies a logical condition defining a memory space, and selects highest priority candidates for the logical memories from the candidates according to priorities. An optimum construction extraction-processing section extracts optimum logical memories satisfying the respective logical conditions from the highest priority candidates such that the limit numbers of usable physical memories and usable registers are satisfied. A circuit description-processing section executes circuit description by using the physical memories and the registers that construct each of the extracted optimum logical memories, to thereby generate a circuit description file.
Public/Granted literature
- US20070180213A1 Memory construction apparatus Public/Granted day:2007-08-02
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