Invention Grant
US07805690B2 Method for generating compiler, simulation, synthesis and test suite from a common processor specification
有权
从通用处理器规范生成编译器,仿真,综合和测试套件的方法
- Patent Title: Method for generating compiler, simulation, synthesis and test suite from a common processor specification
- Patent Title (中): 从通用处理器规范生成编译器,仿真,综合和测试套件的方法
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Application No.: US11865596Application Date: 2007-10-01
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Publication No.: US07805690B2Publication Date: 2010-09-28
- Inventor: John Willis
- Applicant: John Willis
- Applicant Address: US MN Rochester
- Assignee: FTL Systems, Inc.
- Current Assignee: FTL Systems, Inc.
- Current Assignee Address: US MN Rochester
- Agency: Ojanen Law Offices
- Agent Craig J. Lervick; Karuna Ojanen
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A hardware/software design tool converts an electronic design specification and zero or more technology specifications into realization of the electronic design in computer hardware, software and firmware. It compiles design and logic technology specifications into a model which can be utilized for behavioral analysis of logical characteristics. It translates partitions of the design and one or more logic technologies into one or more processor intermediates or binaries suitable for execution on multi-purpose processing units. It translates partitions of the design and logic technology into a collection of cells and interconnects suitable for input to physical design processes such as is required to target a FPGA, ASIC, system-on-a-chip or custom logic. It analyzes behavior of the embedded binaries running on processing units and implementations augmented by additional physical technology and parameters, yielding a more detailed prediction of the resulting hardware/software system behavior when realized through manufacturing.
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