A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring a failure observed image P2 of a semiconductor device, a layout information acquirer 12 for acquiring layout information, and a failure analyzer 13 for analyzing a failure. The failure analyzer 13 extracts candidate nets passing at least one of analysis regions set from the failure observed image, out of a plurality of nets in the semiconductor device, and passage counts of the respective candidate nets through the analysis regions, selects a candidate net with the largest passage count as a first failure net, and selects a second failure net with attention to analysis regions where the first failure net does not pass. This substantializes a semiconductor failure analysis apparatus, failure analysis method, and failure analysis program capable of securely and efficiently performing the analysis of the failure of the semiconductor device using the failure observed image.