Invention Grant
- Patent Title: Apparatus and method to facilitate hierarchical netlist checking
- Patent Title (中): 便于分级网表检查的装置和方法
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Application No.: US11724322Application Date: 2007-03-15
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Publication No.: US07805694B2Publication Date: 2010-09-28
- Inventor: John W. Regnier
- Applicant: John W. Regnier
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dickstein Shapiro LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
An apparatus and method are disclosed which determine locations where verification data should exist in a circuit representation and then propagates verification or circuit properties within a circuit representation. For a hierarchical representation of a circuit, a minimum number of modified circuit entities are created and added to the hierarchical representation such that pertinent critical net and property information is represented at each hierarchical level.
Public/Granted literature
- US20070192755A1 Apparatus and method to facilitate hierarchical netlist checking Public/Granted day:2007-08-16
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