Invention Grant
- Patent Title: Method of manufacturing chip integrated substrate
- Patent Title (中): 芯片集成基板的制造方法
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Application No.: US12123744Application Date: 2008-05-20
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Publication No.: US07807510B2Publication Date: 2010-10-05
- Inventor: Toshio Kobayashi
- Applicant: Toshio Kobayashi
- Applicant Address: JP Nagano-shi, Nagano
- Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee Address: JP Nagano-shi, Nagano
- Agency: Drinker Biddle & Reath LLP
- Priority: JP2007-133947 20070521
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L21/70

Abstract:
There are provided the steps of connecting a chip component 13 to a first substrate 10 through a wire 14, providing an electrode 21 on a second substrate 20, attaching, to the first substrate 10, a molding tool 30 having a protruded portion 31 formed corresponding to an array of a bump connecting pad 12 of the first substrate 10 and a cavity 32 formed corresponding to a region in which the chip component 13 is mounted, thereby forming a first sealing resin 34 for sealing the chip component 13 and the wire 14, bonding the electrode 21 to the bump connecting pad 12 through a solder, thereby bonding the first substrate 10 to the second substrate 20, and filling a second filling resin 40 in a clearance portion between the first substrate 10 and the second substrate 20.
Public/Granted literature
- US20080293189A1 METHOD OF MANUFACTURING CHIP INTEGRATED SUBSTRATE Public/Granted day:2008-11-27
Information query
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