Invention Grant
- Patent Title: Method of fabricating a semiconductor device with a trench isolation structure and resulting semiconductor device
- Patent Title (中): 制造具有沟槽隔离结构和所得半导体器件的半导体器件的方法
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Application No.: US11822470Application Date: 2007-07-06
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Publication No.: US07808031B2Publication Date: 2010-10-05
- Inventor: Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
- Applicant: Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2001-245209 20010813
- Main IPC: H01L29/423
- IPC: H01L29/423

Abstract:
The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.
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