Invention Grant
- Patent Title: Semiconductor device and manufacturing method thereof
- Patent Title (中): 半导体装置及其制造方法
-
Application No.: US12198614Application Date: 2008-08-26
-
Publication No.: US07808078B2Publication Date: 2010-10-05
- Inventor: Keiji Mita
- Applicant: Keiji Mita
- Applicant Address: JP Moriguchi-shi JP Gunma JP Ojiya-shi
- Assignee: Sanyo Electric Co., Ltd.,Sanyo Semiconductor Co., Ltd.,Sanyo Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Sanyo Electric Co., Ltd.,Sanyo Semiconductor Co., Ltd.,Sanyo Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: JP Moriguchi-shi JP Gunma JP Ojiya-shi
- Agency: Morrison & Foerster LLP
- Main IPC: H01L29/00
- IPC: H01L29/00

Abstract:
A semiconductor integrated circuit is reduced in size by suppressing lateral extension of an impurity region when impurities in the impurity region are thermally diffused in a semiconductor substrate. A second photoresist is formed on an insulation film. The second photoresist is formed to have second openings K2 on both sides of a P-type impurity region so that the second openings K2 partially overlap the P-type impurity region. The insulation film is etched off together with an underlying surface of the semiconductor substrate using the second photoresist as a mask so as to remove the P-type impurity region partially. Then, phosphorus ions (P+) are implanted into the surface of the semiconductor substrate in the etched-off regions using the second photoresist as a mask to form N-type impurity regions that are adjacent the P-type impurity region. After removing the second photoresist, the impurities in the P-type impurity region and the impurities in the N-type impurity region are thermally diffused.
Public/Granted literature
- US20100052101A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Public/Granted day:2010-03-04
Information query
IPC分类: