Invention Grant
- Patent Title: Determining overlay error using an in-chip overlay target
- Patent Title (中): 使用片内覆盖目标确定覆盖错误
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Application No.: US12340563Application Date: 2008-12-19
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Publication No.: US07808643B2Publication Date: 2010-10-05
- Inventor: Nigel P. Smith , Kevin E Heidrich
- Applicant: Nigel P. Smith , Kevin E Heidrich
- Applicant Address: US CA Milpitas
- Assignee: Nanometrics Incorporated
- Current Assignee: Nanometrics Incorporated
- Current Assignee Address: US CA Milpitas
- Agency: Silicon Valley Patent Group LLP
- Main IPC: G01N21/55
- IPC: G01N21/55

Abstract:
Overlay error between two layers on a substrate is measured using an image of an overlay target in an active area of a substrate. The overlay target may be active features, e.g., structures that cause the device to function as desired when manufacturing is complete. The active features may be permanent structures or non-permanent structures, such as photoresist, that are used define the permanent structures during manufacturing. The image of the overlay target is analyzed by measuring the light intensity along one or more scan lines and calculating a symmetry values for the scan lines. Using the symmetry values, the overlay error can be determined.
Public/Granted literature
- US20090116014A1 Determining Overlay Error Using an In-chip Overlay Target Public/Granted day:2009-05-07
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