Invention Grant
- Patent Title: High performance multilevel cache hierarchy
- Patent Title (中): 高性能多级缓存层次结构
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Application No.: US11779784Application Date: 2007-07-18
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Publication No.: US07809889B2Publication Date: 2010-10-05
- Inventor: Robert Nychka , Janardan Prasad , Nilesh Acharya , Aditya Rawal , Ambar Nawaz
- Applicant: Robert Nychka , Janardan Prasad , Nilesh Acharya , Aditya Rawal , Ambar Nawaz
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Ronald O. Neerings; Wade James Brady, III; Frederick J. Telecky, Jr.
- Main IPC: G06F12/08
- IPC: G06F12/08

Abstract:
A digital system is provided with a hierarchical memory system having at least a first and second level cache and a higher level memory. If a requested data item misses in both the first cache level and in the second cache level, a line of data containing the requested data is obtained from a higher level of the hierarchical memory system. The line of data is allocated to both the first cache level and to the second cache level simultaneously.
Public/Granted literature
- US20090024796A1 High Performance Multilevel Cache Hierarchy Public/Granted day:2009-01-22
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