Invention Grant
- Patent Title: System and method for providing a high-speed message passing interface for barrier operations in a multi-tiered full-graph interconnect architecture
- Patent Title (中): 用于在多层全图互连架构中提供用于屏障操作的高速消息传递接口的系统和方法
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Application No.: US11845225Application Date: 2007-08-27
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Publication No.: US07809970B2Publication Date: 2010-10-05
- Inventor: Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
- Applicant: Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Francis Lammes; Stephen J. Walder, Jr.; Diana R. Gerhardt
- Main IPC: G06F1/12
- IPC: G06F1/12 ; G06F1/32

Abstract:
A method, computer program product, and system are provided performing a Message Passing Interface (MPI) job. A first processor chip receives a set of arrival signals from a set of processor chips executing tasks of the MPI job in the data processing system. The arrival signals identify when a processor chip executes a synchronization operation for synchronizing the tasks for the MPI job. Responsive to receiving the set of arrival signals from the set of processor chips, the first processor chip identifies a fastest processor chip of the set of processor chips whose arrival signal arrived first. An operation of the fastest processor chip is modified based on the identification of the fastest processor chip. The set of processor chips comprises processor chips that are in one of a same processor book or a different processor book of the data processing system.
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