Invention Grant
US07810003B2 Method of generating test clock signal and test clock signal generator for testing semiconductor devices
有权
产生测试时钟信号的方法和用于测试半导体器件的测试时钟信号发生器
- Patent Title: Method of generating test clock signal and test clock signal generator for testing semiconductor devices
- Patent Title (中): 产生测试时钟信号的方法和用于测试半导体器件的测试时钟信号发生器
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Application No.: US11862305Application Date: 2007-09-27
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Publication No.: US07810003B2Publication Date: 2010-10-05
- Inventor: Han-Soo Seong
- Applicant: Han-Soo Seong
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Volentine & Whitt, P.L.L.C.
- Priority: KR10-2006-0104445 20061026
- Main IPC: G01R31/3177
- IPC: G01R31/3177 ; G01R31/30
Abstract:
A system and method of generating a test clock signal for scan testing of a main circuit in a semiconductor device includes receiving an external clock signal and a control signal and generating a gated clock signal by gating an internal clock signal based on the control signal. The internal clock signal has a frequency higher than a frequency of the external clock signal. One of the external clock signal and the gated clock signal is selectively output based on the control signal.
Public/Granted literature
- US20080103719A1 METHOD OF GENERATING TEST CLOCK SIGNAL AND TEST CLOCK SIGNAL GENERATOR FOR TESTING SEMICONDUCTOR DEVICES Public/Granted day:2008-05-01
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