Invention Grant
US07812397B2 Ultra thin channel (UTC) MOSFET structure formed on BOX regions having different depths and different thicknesses beneath the UTC and source/drain regions and method of manufacture thereof
有权
在UTC和源极/漏极区域下方形成具有不同深度和不同厚度的BOX区域上的超薄沟道（UTC）MOSFET结构及其制造方法
- Patent Title: Ultra thin channel (UTC) MOSFET structure formed on BOX regions having different depths and different thicknesses beneath the UTC and source/drain regions and method of manufacture thereof
- Patent Title (中): 在UTC和源极/漏极区域下方形成具有不同深度和不同厚度的BOX区域上的超薄沟道（UTC）MOSFET结构及其制造方法
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Application No.: US12166285Application Date: 2008-07-01
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Publication No.: US07812397B2Publication Date: 2010-10-12
- Inventor: Changguo Cheng , Dureseti Chidambarrao , Brian Joseph Greene , Jack A. Mandelman , Kern Rim
- Applicant: Changguo Cheng , Dureseti Chidambarrao , Brian Joseph Greene , Jack A. Mandelman , Kern Rim
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent H. Daniel Schnurmann; Graham S. Jones
- Main IPC: H01L21/336
- IPC: H01L21/336
Abstract:
A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. A UT SOI channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A BOX1 region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a BOX2 region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.
Public/Granted literature
Information query
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