Invention Grant
- Patent Title: Semiconductor device comprising multi-layer rectangular gate electrode surrounded on four sides by sidewall spacer and implantation regions
- Patent Title (中): 半导体器件包括通过侧壁间隔物和注入区四面包围的多层矩形栅电极
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Application No.: US11693408Application Date: 2007-03-29
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Publication No.: US07812399B2Publication Date: 2010-10-12
- Inventor: Takashi Yuda
- Applicant: Takashi Yuda
- Applicant Address: JP Tokyo
- Assignee: Oki Semiconductor Co., Ltd.
- Current Assignee: Oki Semiconductor Co., Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Rabin & Berdo, PC
- Priority: JP2006-100891 20060331
- Main IPC: H01L23/62
- IPC: H01L23/62

Abstract:
The present invention provides a semiconductor device which includes a gate electrode shaped in the form of an approximately quadrangular prism, including a laminated body of a gate oxide layer, a gate polysilicon layer and a gate silicon nitride layer provided in a first conduction type substrate, a second conduction type implantation region provided in a region outside the gate electrode, a sidewall that exposes a top face of the gate electrode and is formed by laminating a sidewall mask oxide layer covering side surfaces, an electron storage nitride layer and a sidewall silicon oxide layer, and a source/drain diffusion layer provided in the first conduction type substrate exposed from the gate electrode and the sidewall.
Public/Granted literature
- US20070228483A1 Semiconductor device and Manufacturing method thereof Public/Granted day:2007-10-04
Information query
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