Invention Grant
- Patent Title: Interconnect in low-k interlayer dielectrics
- Patent Title (中): 互连在低k层间电介质
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Application No.: US12139848Application Date: 2008-06-16
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Publication No.: US07812455B2Publication Date: 2010-10-12
- Inventor: Sean King , Ruth Brain
- Applicant: Sean King , Ruth Brain
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Laleh Jalali
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40

Abstract:
A method for forming deep lithographic interconnects between a first metal and a second metal is provided. The method comprises depositing a first insulator layer on a semiconductor substrate; etching the first insulator layer at a selected location to provide at least a first via to the semiconductor substrate; depositing the first metal on the semiconductor substrate to form at least a first metal contact plug in the first via in contact with the semiconductor substrate; treating the semiconductor substrate with an in-situ plasma of a nitrogen containing gas wherein the plasma forms a nitride layer of the first metal at least capping a top surface of the first metal plug in the first via; and forming a second metal contact to the metal nitride layer capping at least the top surface of the first metal plug.
Public/Granted literature
- US20090309227A1 FABRICATION OF INTERCONNECTS IN LOW-K INTERLAYER DIELECTRICS Public/Granted day:2009-12-17
Information query
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