A frequency synthesizer includes a phase locked loop (PLL) for generating a desired frequency. The PLL includes two loop filters. A characterization circuit is included, which is configured to receive a digital word for characterizing the PLL and provide a pre-charge value for pre-charging one of the loop filters to generate the desired frequency. A successive approximation analog to digital (A/D) converter is coupled between the loop filters and the characterization circuit, for providing both (a) the digital word to the characterization circuit, and (b) the pre-charge value to the selected loop filter. The digital word includes n-bits ranging in values from a most significant bit (MSB) to a least significant bit (LSB), and the pre-charge value is formed by the n-bits. The successive approximation A/D converter includes a successive approximation register (SAR) for forming the digital word, and a digital to analog (D/A) converter for forming the pre-charge value. The successive approximation A/D converter includes a comparator for comparing (a) a value corresponding to a loop filter voltage with (b) an analog value formed by a bit of the digital word.