Invention Grant
US07812845B2 PC-based computing system employing a silicon chip implementing parallelized GPU-driven pipelines cores supporting multiple modes of parallelization dynamically controlled while running a graphics application
有权
基于PC的计算系统采用硅芯片,实现并行化GPU驱动的管线核心,支持在运行图形应用程序时动态控制的多种并行模式
- Patent Title: PC-based computing system employing a silicon chip implementing parallelized GPU-driven pipelines cores supporting multiple modes of parallelization dynamically controlled while running a graphics application
- Patent Title (中): 基于PC的计算系统采用硅芯片,实现并行化GPU驱动的管线核心,支持在运行图形应用程序时动态控制的多种并行模式
-
Application No.: US11978226Application Date: 2007-10-26
-
Publication No.: US07812845B2Publication Date: 2010-10-12
- Inventor: Reuven Bakalash , Offir Remez , Efi Fogel
- Applicant: Reuven Bakalash , Offir Remez , Efi Fogel
- Applicant Address: IL Kfar Netter
- Assignee: Lucid Information Technology, Ltd.
- Current Assignee: Lucid Information Technology, Ltd.
- Current Assignee Address: IL Kfar Netter
- Agent Thomas J. Perkowski, Esq., P.C.
- Main IPC: G06F15/80
- IPC: G06F15/80 ; G06F15/16 ; G06F13/14 ; G06T15/00

Abstract:
A PC-based computing system employing a silicon chip implementing parallelized GPU-driven pipelines cores supporting multiple modes of parallelization dynamically controlled while running a graphics application. The PC-based computing system includes system memory for storing software graphics applications, software drivers and graphics libraries, and an operating system (OS), stored in the system memory, and a central processing unit (CPU), for executing the OS, graphics applications, drivers and graphics libraries. The system also includes a CPU/memory interface module and a CPU bus. The routing unit (i) routes the stream of geometrical data and graphic commands from the graphics application to one or more of the GPU-driven pipeline cores, and (ii) routes pixel data output from one or more of GPU-driven pipeline cores during the composition of frames of pixel data corresponding to final images for display on the display surface. The control unit accepts commands from the software multi-pipe drivers, and controls components within the silicon chip, including the routing unit. The profiling unit profiles the performance of the GPU-driven pipeline cores and feeds back performance data to the software multi-pipe drivers, for dynamically determining and controlling the mode of parallelization during the generation of each frame of pixel data, while running a graphics application.
Public/Granted literature
Information query