A semiconductor memory device includes first to third resistive memory elements, a first transistor having a first gate electrode, first and second source/drain electrodes, the first source/drain electrode being connected to one terminal of the first resistive memory element, and the second source/drain electrode being connected to one terminal of the third resistive memory element, a second transistor having a second gate electrode, third and fourth source/drain electrodes, the third source/drain electrode being connected to one terminal of the second resistive memory element, and the fourth source/drain electrode being connected to one terminal of the third resistive memory element, a first bit line connected to the other terminal of the third resistive memory element, a second bit line connected to the other terminal of each of the first and second resistive memory elements, and first and second word lines connected to each of the first and second gate electrodes.