Invention Grant
- Patent Title: Semiconductor memory device having plural word lines arranged at narrow pitch and manufacturing method thereof
- Patent Title (中): 具有窄间距排列的多个字线的半导体存储器件及其制造方法
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Application No.: US12178089Application Date: 2008-07-23
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Publication No.: US07813179B2Publication Date: 2010-10-12
- Inventor: Norihisa Arai
- Applicant: Norihisa Arai
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2007-192278 20070724
- Main IPC: G11C16/04
- IPC: G11C16/04

Abstract:
A semiconductor memory device includes a memory cell array which includes at least one memory unit having a preset number of memory cell transistors and a selection gate transistor on a source side, a preset number of word lines respectively connected to control gates of the preset number of memory cell transistors, and a selection gate line on a source side connected to a gate electrode of the selection gate transistor on the source side. In the semiconductor memory device, a distance C between the selection gate line at least on the source side and one of the word lines adjacent thereto is set to n*A+(n−1)B, where n is an integer greater than or equal to 2, A indicates the pitch between adjacent ones of the preset number of word lines, and B indicates the width of each of the preset number of word lines.
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