Invention Grant
- Patent Title: Built in self test for input/output characterization
- Patent Title (中): 内置自检输入/输出表征
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Application No.: US12117268Application Date: 2008-05-08
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Publication No.: US07814386B2Publication Date: 2010-10-12
- Inventor: John Joseph Seibold , Vinay B. Jayaram , Elie Torbey
- Applicant: John Joseph Seibold , Vinay B. Jayaram , Elie Torbey
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Dawn V. Stephens; Wade James Brady, III; Frederick J. Telecky, Jr.
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
A test system in an integrated circuit includes at least one boundary scan cell. The boundary scan cell includes a first storage element and a second storage element connected in series with the first storage element. The boundary scan cell also includes test logic configured to provide a test completion signal indicative of completion of a respective test based on a comparison of an output of the first storage element relative to test value (TVALUE). The output of the first storage element is provided to the input of the second storage element unchanged during a first operating state and, depending on the test completion signal, an inverted version of the output of the first storage element can be provided to the input of the second storage element during a second operating state. A bi-directional element is connected to receive the output of the second storage element and to feed the output of the second storage element back to an input of the first storage element.
Public/Granted literature
- US20090113264A1 BUILT IN SELF TEST FOR INPUT/OUTPUT CHARACTERIZATION Public/Granted day:2009-04-30
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