Invention Grant
- Patent Title: Semiconductor structure including laminated isolation region
- Patent Title (中): 半导体结构包括层压隔离区
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Application No.: US12110633Application Date: 2008-06-20
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Publication No.: US07816760B2Publication Date: 2010-10-19
- Inventor: Zhijiong Luo , Huilong Zhu
- Applicant: Zhijiong Luo , Huilong Zhu
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent H. Daniel Schnurmann
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A semiconductor structure and a related method for fabrication thereof include an isolation region located within an isolation trench within a semiconductor substrate. The isolation region comprises; (1) a lower lying dielectric plug layer recessed within the isolation trench; (2) a U shaped dielectric liner layer located upon the lower lying dielectric plug layer and partially filling the recess; and (3) an upper lying dielectric plug layer located upon the U shaped dielectric liner layer and completely filling the recess. The isolation region provides for sidewall coverage of the isolation trench, thus eliminating some types of leakage paths.
Public/Granted literature
- US20080246112A1 SEMICONDUCTOR STRUCTURE INCLUDING LAMINATED ISOLATION REGION Public/Granted day:2008-10-09
Information query
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