A termination impedance control circuit is capable of controlling a dynamic ODT operation in a DDR3-level semiconductor memory device. The termination impedance control circuit includes a counter unit configured to count an external clock and an internal clock to output a first code and a second code, respectively, and a dynamic controller configured to enable a dynamic termination operation by comparing the first code with the second code in response to a write command and disable the dynamic termination operation after a predetermined time, determined according to a burst length, has lapsed after the dynamic termination operation is enabled.