Invention Grant
US07816958B2 Means to reduce the PLL phase bump caused by a missing clock pulse
有权
意味着减少由缺失的时钟脉冲引起的PLL相位凸起
- Patent Title: Means to reduce the PLL phase bump caused by a missing clock pulse
- Patent Title (中): 意味着减少由缺失的时钟脉冲引起的PLL相位凸起
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Application No.: US11744420Application Date: 2007-05-04
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Publication No.: US07816958B2Publication Date: 2010-10-19
- Inventor: James Toner Sundby
- Applicant: James Toner Sundby
- Applicant Address: US CA Fremont
- Assignee: Exar Corporation
- Current Assignee: Exar Corporation
- Current Assignee Address: US CA Fremont
- Agency: Townsend and Townsend and Crew LLP
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
A PLL includes control circuitry adapted to detect missing pulses of a reference clock and to control an output voltage of a charge pump disposed in the PLL accordingly. A signal generated in response to the detection of a missing pulse is pulse-width limited and applied to the charge pump during a first period. The detection of the pulse-width limited signal is used to generate a first slew signal that is also pulse-width limited and applied to the charge pump during a second period. The detection of the first slew signal is used to generate a second slew signal that is also pulse-width limited and applied to the charge pump during a third period. The amount of current supplied by the charge pump during the second charging period is equal to a sum of currents withdrawn by the charge pump during the first and third time periods.
Public/Granted literature
- US20080273648A1 Means To Reduce The PLL Phase Bump Caused By A Missing Clock Pulse Public/Granted day:2008-11-06
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