Invention Grant
- Patent Title: Processor bus for performance monitoring with digests
- Patent Title (中): 处理器总线,用于通过摘要进行性能监控
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Application No.: US12186481Application Date: 2008-08-05
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Publication No.: US07818624B2Publication Date: 2010-10-19
- Inventor: Hillery C. Hunter , Ravi Nair
- Applicant: Hillery C. Hunter , Ravi Nair
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Main IPC: G06F11/00
- IPC: G06F11/00

Abstract:
A method for monitoring event occurrences from a plurality of processor units at a centralized location via a dedicated bus coupled between the plurality of processor units and the centralized location. In particular, the method comprises receiving, at the centralized location, data indicative of cumulative events occurring at one of the processor units, and storing the data in a first temporary memory. The data is then stored in a register based on a tag identifier affixed to the data in an instance where the tag identifier provides indicia of one of the plurality of processor units.
Public/Granted literature
- US20080294944A1 PROCESSOR BUS FOR PERFORMANCE MONITORING WITH DIGESTS Public/Granted day:2008-11-27
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