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US07818624B2 Processor bus for performance monitoring with digests 失效
处理器总线,用于通过摘要进行性能监控

Processor bus for performance monitoring with digests
Abstract:
A method for monitoring event occurrences from a plurality of processor units at a centralized location via a dedicated bus coupled between the plurality of processor units and the centralized location. In particular, the method comprises receiving, at the centralized location, data indicative of cumulative events occurring at one of the processor units, and storing the data in a first temporary memory. The data is then stored in a register based on a tag identifier affixed to the data in an instance where the tag identifier provides indicia of one of the plurality of processor units.
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