Invention Grant
- Patent Title: Hierarchical test response compaction for a plurality of logic blocks
- Patent Title (中): 多个逻辑块的分层测试响应压缩
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Application No.: US11903913Application Date: 2007-09-25
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Publication No.: US07818642B2Publication Date: 2010-10-19
- Inventor: Kee Sup Kim , Ming Zhang , Avi Kovacs
- Applicant: Kee Sup Kim , Ming Zhang , Avi Kovacs
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G01R31/3177
- IPC: G01R31/3177 ; G01R31/302
Abstract:
In one embodiment, the present invention includes first level matrices, each including m input terminals and n output terminals, each coupled to a processor core, and second level matrices each coupled to the n output terminals of one of the first level matrices, where each of the second level matrices has n input terminals and p output terminals, and the p output terminals of the second level matrices correspond to a compacted output from the multiple processor cores. Other embodiments are described and claimed.
Public/Granted literature
- US20090083599A1 Hierarchical test response compaction for a plurality of logic blocks Public/Granted day:2009-03-26
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