Invention Grant
US07821073B2 Patterned backside stress engineering for transistor performance optimization
有权
用于晶体管性能优化的图案化背侧应力工程
- Patent Title: Patterned backside stress engineering for transistor performance optimization
- Patent Title (中): 用于晶体管性能优化的图案化背侧应力工程
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Application No.: US12061935Application Date: 2008-04-03
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Publication No.: US07821073B2Publication Date: 2010-10-26
- Inventor: Gilroy J. Vandentop , Rajashree Baskaran
- Applicant: Gilroy J. Vandentop , Rajashree Baskaran
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Dave L. Guglielmi
- Main IPC: H01L27/092
- IPC: H01L27/092
Abstract:
Some embodiments of the present invention include selectively inducing back side stress opposite transistor regions to optimize transistor performance.
Public/Granted literature
- US20080237729A1 PATTERNED BACKSIDE STRESS ENGINEERING FOR TRANSISTOR PERFORMANCE OPTIMIZATION Public/Granted day:2008-10-02
Information query
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