Invention Grant
US07829168B2 Methods for inspecting and optionally reworking summed photolithography patterns resulting from plurally-overlaid patterning steps during mass production of semiconductor devices
有权
用于在大量生产半导体器件期间检查和可选地重新绘制由多重重叠的图案化步骤产生的总光刻图案的方法
- Patent Title: Methods for inspecting and optionally reworking summed photolithography patterns resulting from plurally-overlaid patterning steps during mass production of semiconductor devices
- Patent Title (中): 用于在大量生产半导体器件期间检查和可选地重新绘制由多重重叠的图案化步骤产生的总光刻图案的方法
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Application No.: US11943931Application Date: 2007-11-21
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Publication No.: US07829168B2Publication Date: 2010-11-09
- Inventor: Xinyu Zhang , Feng-Hong Zhang
- Applicant: Xinyu Zhang , Feng-Hong Zhang
- Applicant Address: SG Singapore
- Assignee: ProMOS Technologies Pte. Ltd.
- Current Assignee: ProMOS Technologies Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Haynes and Boone, LLP
- Main IPC: B32B3/02
- IPC: B32B3/02 ; B32B3/10
Abstract:
A batch of wafers is temporarily stalled during a Double Pattern Technology (DPT) process before a temporary representation of a second of to-be-overlaid patterns is permanently combined with a first of the patterns. Sampled ones of the stalled wafers are inspected to determine if sufficiently close alignment is present between the two patterns. If excessive misalignment is detected (e.g., by SEM microscopy), the second but still temporary pattern representation is erased from all wafers of the batch and the batch is routed for rework and corrected reestablishment of the temporary representation of the second of to-be-overlaid patterns.
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