Invention Grant
- Patent Title: Wafer level stacked die packaging
- Patent Title (中): 晶圆级堆叠模包装
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Application No.: US11874083Application Date: 2007-10-17
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Publication No.: US07829379B2Publication Date: 2010-11-09
- Inventor: Thomas M. Goida
- Applicant: Thomas M. Goida
- Applicant Address: US MA Norwood
- Assignee: Analog Devices, Inc.
- Current Assignee: Analog Devices, Inc.
- Current Assignee Address: US MA Norwood
- Agency: Sunstein Kann Murphy & Timbers LLP
- Main IPC: H01L21/00
- IPC: H01L21/00
Abstract:
A method of manufacturing semiconductor devices by applying a pattern of adhesive pads on an active surface of a semiconductor wafer, the semiconductor wafer product so made and a stacked die package in which an adhesive wall leaves an air gap atop a bottom die. The wall may be in the form of a ring of adhesive about a central hollow area. The wafer carrying the pattern of adhesive pads on its active surface is singulated into individual dies, each die having an adhesive pad thereon. The bottom die is attached to a base with an adhesive which cures without curing the adhesive pad.
Public/Granted literature
- US20090102060A1 Wafer Level Stacked Die Packaging Public/Granted day:2009-04-23
Information query
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