Method of making a semiconductor memory array of floating gate memory cells with program/erase and select gates

Invention Grant

US07829404B2 Method of making a semiconductor memory array of floating gate memory cells with program/erase and select gates 有权

Title translation: 制造具有编程/擦除和选择栅极的浮动栅极存储单元的半导体存储器阵列的方法

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Patent Title: Method of making a semiconductor memory array of floating gate memory cells with program/erase and select gates
Patent Title (中): 制造具有编程/擦除和选择栅极的浮动栅极存储单元的半导体存储器阵列的方法
Application No.: US11950345

Application Date: 2007-12-04
Publication No.: US07829404B2

Publication Date: 2010-11-09
Inventor: Pavel Klinger , Amitay Levi
Applicant: Pavel Klinger , Amitay Levi
Applicant Address: US CA Sunnyvale
Assignee: Silicon Storage Technology, Inc.
Current Assignee: Silicon Storage Technology, Inc.
Current Assignee Address: US CA Sunnyvale
Agency: DLA Piper LLP (US)
Main IPC: H01L21/8238
IPC: H01L21/8238

Method of making a semiconductor memory array of floating gate memory cells with program/erase and select gates

Abstract:

A memory device, and method of making and operating the same, including a substrate of semiconductor material of a first conductivity type, first and second spaced apart regions in the substrate of a second conductivity type with a channel region therebetween, an electrically conductive floating gate having a first portion disposed over and insulated from the channel region and a second portion disposed over and insulated from the first region and including a sharpened edge, an electrically conductive P/E gate having a first portion disposed over and insulated from the first region and a second portion extending up and over the floating gate second portion and insulated therefrom by a first layer of insulation material, and an electrically conductive select gate having a first portion disposed laterally adjacent to the floating gate and disposed over and insulated from the channel region.

Abstract(Chinese):

存储器件及其制造和操作方法，包括第一导电类型的半导体材料的衬底，第二导电类型的衬底中的第一和第二间隔开的区域，其间具有沟道区，导电浮置栅极具有设置在所述沟道区域上方并与所述沟道区域绝缘的第一部分和设置在所述第一区域上并与所述第一区域绝缘的第二部分，并且包括锐化边缘;导电P / E门，其具有设置在所述第一区域上方并与所述第一区域绝缘的第一部分，第二部分，其在浮动栅极第二部分上方和上方延伸并且通过第一绝缘材料层与其绝缘;以及导电选择栅极，其具有横向邻近所述浮动栅极设置并设置在所述沟道区域上并与所述沟道区域绝缘的第一部分。

Public/Granted literature

US20080084744A1 METHOD OF MAKING AND OPERATING A SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH PROGRAM/ERASE AND SELECT GATES Public/Granted day:2008-04-10

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8238	........互补场效应晶体管，例如CMOS