Invention Grant
- Patent Title: Method of forming a wiring structure in a semiconductor device
- Patent Title (中): 在半导体器件中形成布线结构的方法
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Application No.: US12172836Application Date: 2008-07-14
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Publication No.: US07829458B2Publication Date: 2010-11-09
- Inventor: Jae-Choel Paik
- Applicant: Jae-Choel Paik
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Volentine & Whitt, P.L.L.C.
- Priority: KR10-2007-0071728 20070718
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
A wiring structure includes a first insulation layer located on a substrate, and first and second plugs located on the substrate and extending through the first insulation layer. The first plug includes an upper peripheral portion that defines a recess and the second plug is adjacent to the first plug. A second insulation layer is located on the first insulation layer, the first plug and the second plug. A bit line structure is located on the second insulation layer and is electrically connected to the first plug. A protection spacer is located on the recess of the first plug and a sidewall of an opening in the second insulation layer. The opening exposes the recess of the first plug, the second plug and the sidewall of the bit line structure. A pad is located in the opening and contacts the second plug.
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