Invention Grant
- Patent Title: Planarization method using hybrid oxide and polysilicon CMP
- Patent Title (中): 使用混合氧化物和多晶硅CMP的平面化方法
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Application No.: US11551390Application Date: 2006-10-20
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Publication No.: US07829464B2Publication Date: 2010-11-09
- Inventor: David Matsumoto , Vidyut Gopal
- Applicant: David Matsumoto , Vidyut Gopal
- Applicant Address: US CA Sunnyvale KY Grand Cayman
- Assignee: Spansion LLC,GlobalFoundries Inc.
- Current Assignee: Spansion LLC,GlobalFoundries Inc.
- Current Assignee Address: US CA Sunnyvale KY Grand Cayman
- Agency: Harrity & Harrity, LLP
- Main IPC: H01L21/461
- IPC: H01L21/461 ; H01L21/302
Abstract:
A method of planarizing a semiconductor device is provided. The semiconductor device includes a substrate, first and second components provided on the surface of the substrate, and a first material provided between and above the first and second components. The first component has a height greater than a height of the second component. The method includes performing a first polishing step on the semiconductor device to remove the first material above a top surface of the first component, to remove the first material above a top surface of the second component, and to level the top surface of the first component. The method also includes performing a second polishing step on the semiconductor device to planarize the top surfaces of the first and second components.
Public/Granted literature
- US20080096388A1 PLANARIZATION METHOD USING HYBRID OXIDE AND POLYSILICON CMP Public/Granted day:2008-04-24
Information query
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