Invention Grant
US07829985B2 BGA package having half-etched bonding pad and cut plating line and method of fabricating same
有权
BGA封装具有半蚀刻焊盘和切割电镀线及其制造方法
- Patent Title: BGA package having half-etched bonding pad and cut plating line and method of fabricating same
- Patent Title (中): BGA封装具有半蚀刻焊盘和切割电镀线及其制造方法
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Application No.: US12315721Application Date: 2008-12-04
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Publication No.: US07829985B2Publication Date: 2010-11-09
- Inventor: Hyo Soo Lee , Sung Eun Park
- Applicant: Hyo Soo Lee , Sung Eun Park
- Applicant Address: KR Kyunggi-Do
- Assignee: Samsung Electro-Mechanics Co., Ltd.
- Current Assignee: Samsung Electro-Mechanics Co., Ltd.
- Current Assignee Address: KR Kyunggi-Do
- Agency: Fish & Richardson P.C.
- Priority: KR10-2004-0116799 20041230
- Main IPC: H01L23/495
- IPC: H01L23/495

Abstract:
A ball grid array (BGA) package having a half-etched bonding pad and a cut plating line and a method of fabricating the same. In the BGA package, the plating line is cut to form a predetermined uneven bonding pad using half-etching, thereby increasing the contact area between the bonding pad and a solder ball. The BGA package includes a first external layer having a first circuit pattern and a wire bonding pad pattern wherein a chip is connected to a wire bonding pad using wire bonding. A second external layer includes a second circuit pattern, a cut plating line pattern, and a half-etched uneven solder ball pad pattern. In the second external layer, another chip is mounted on a solder ball pad. An insulating layer having a through hole interposed between the first and second external layers and electrically connects the first and second external layers therethrough.
Public/Granted literature
- US20090093110A1 BGA package having half-etched bonding pad and cut plating line and method of fabricating same Public/Granted day:2009-04-09
Information query
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