Invention Grant
- Patent Title: Interconnect for chip level power distribution
- Patent Title (中): 互连芯片级配电
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Application No.: US11732594Application Date: 2007-04-04
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Publication No.: US07829997B2Publication Date: 2010-11-09
- Inventor: Kevin J. Hess , Chu-Chung Lee , James W. Miller
- Applicant: Kevin J. Hess , Chu-Chung Lee , James W. Miller
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: H01L23/52
- IPC: H01L23/52
Abstract:
A semiconductor device (601) is provided which comprises a substrate (603); a semiconductor device (605) disposed on said substrate and having a first major surface; a first metal strap (615) which is in electrical contact with said substrate and which is adapted to provide power to a first region (608) of said semiconductor device; and a second metal strap (616) which is in electrical contact with said substrate and which is adapted to provide ground to a second region (609) of said semiconductor device.
Public/Granted literature
- US20080246165A1 Novel interconnect for chip level power distribution Public/Granted day:2008-10-09
Information query
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