Invention Grant
- Patent Title: Method and apparatus for universal program controlled bus architecture
- Patent Title (中): 通用程控总线架构的方法和装置
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Application No.: US12401055Application Date: 2009-03-10
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Publication No.: US07830173B2Publication Date: 2010-11-09
- Inventor: Peter M. Pani , Benjamin S. Ting
- Applicant: Peter M. Pani , Benjamin S. Ting
- Applicant Address: US CA Mountain View
- Assignee: Actel Corporation
- Current Assignee: Actel Corporation
- Current Assignee Address: US CA Mountain View
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H03K19/177
- IPC: H03K19/177

Abstract:
An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality of functional blocks receiving inputs and transmitting outputs. The integrated circuit may also include a programmable interconnections subsystem to cascade the megacells. The megacells are coupled to the programmable logic array.
Public/Granted literature
- US20090174431A1 METHOD AND APPARATUS FOR UNIVERSAL PROGRAM CONTROLLED BUS ARCHITECTURE Public/Granted day:2009-07-09
Information query
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