Invention Grant
US07830173B2 Method and apparatus for universal program controlled bus architecture 失效
通用程控总线架构的方法和装置

Method and apparatus for universal program controlled bus architecture
Abstract:
An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality of functional blocks receiving inputs and transmitting outputs. The integrated circuit may also include a programmable interconnections subsystem to cascade the megacells. The megacells are coupled to the programmable logic array.
Information query
Patent Agency Ranking
0/0