A DLL (delay locked loop) circuit includes a first variable delay circuit, a pair of second variable delay circuits and a first synthesis circuit. The first variable delay circuit outputs signals of different delayed time values from each of first and second clock transitions. The pair of second variable delay circuits receive the signals from the first variable delay circuit, and the first synthesis circuit synthesizes output signals of the pair of second variable delay circuits to output the resulting synthesized signal. Each of the pair of second variable delay circuits includes a pair one-shot pulse generating circuits that generate one-shot pulses from the signals from the first variable delay circuit, a pair latch circuits, and a second synthesis circuit. The second synthesis circuit receives the set outputs of the latch circuits to output a signal which is a synthesis at a preset synthesis ratio.