Invention Grant
- Patent Title: NAND based resistive sense memory cell architecture
- Patent Title (中): 基于NAND的电阻式读写单元架构
-
Application No.: US12269656Application Date: 2008-11-12
-
Publication No.: US07830693B2Publication Date: 2010-11-09
- Inventor: Harry Hongyue Liu , Haiwen Xi , Antoine Khoueir , Song Xue
- Applicant: Harry Hongyue Liu , Haiwen Xi , Antoine Khoueir , Song Xue
- Applicant Address: US CA Scotts Valley
- Assignee: Seagate Technology LLC
- Current Assignee: Seagate Technology LLC
- Current Assignee Address: US CA Scotts Valley
- Agency: Fellers, Snider, et al.
- Main IPC: G11C5/02
- IPC: G11C5/02

Abstract:
Various embodiments are directed to an apparatus comprising a semiconductor memory array with non-volatile memory unit cells arranged into a NAND block. Each of the unit cells comprises a resistive sense element connected in parallel with a switching element. The resistive sense elements are connected in series to form a first serial path, and the switching elements are connected in series to form a second serial path parallel to the first serial path. Each resistive sense element is serially connected to an adjacent resistive sense element in the block by a tortuous conductive path having a portion that extends substantially vertically between said elements to provide operational isolation therefor.
Public/Granted literature
- US20100118579A1 Nand Based Resistive Sense Memory Cell Architecture Public/Granted day:2010-05-13
Information query