Invention Grant
US07830713B2 Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array
有权
位线栅晶体管结构,用于多层双面非易失性存储单元NAND闪存阵列
- Patent Title: Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array
- Patent Title (中): 位线栅晶体管结构,用于多层双面非易失性存储单元NAND闪存阵列
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Application No.: US12075677Application Date: 2008-03-13
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Publication No.: US07830713B2Publication Date: 2010-11-09
- Inventor: Peter Wung Lee , Fu-Chang Hsu
- Applicant: Peter Wung Lee , Fu-Chang Hsu
- Applicant Address: US CA San Jose
- Assignee: Aplus Flash Technology, Inc.
- Current Assignee: Aplus Flash Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Saile Ackerman LLC
- Agent Stephen B. Ackerman; Billy Knowles
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
A nonvolatile memory structure with pairs of serially connected select transistors connected to the top and optionally to the bottom of NAND series strings of groups of the dual-sided charge-trapping nonvolatile memory cells for controlling connection of the NAND series string to an associated bit line. A first of the serially connected select transistors has an implant to make a threshold voltage of the implanted first serially connected select transistor different from a non-implanted second serially connected select transistor. The pair of serially connected top select transistors is connected to a first of two associated bit lines. Optionally, the NAND nonvolatile memory strings further is connected a pair of serially connected bottom select transistors that is connected to the second associated bit line.
Public/Granted literature
- US20080225594A1 Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array Public/Granted day:2008-09-18
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