Invention Grant
- Patent Title: Semiconductor integrated circuit device featuring processed minimum circuit pattern, and design method therefor
- Patent Title (中): 具有加工最小电路图案的半导体集成电路器件及其设计方法
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Application No.: US11950549Application Date: 2007-12-05
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Publication No.: US07831939B2Publication Date: 2010-11-09
- Inventor: Yoshihisa Matsubara
- Applicant: Yoshihisa Matsubara
- Applicant Address: JP Kanagawa
- Assignee: NEC Electronics Corporation
- Current Assignee: NEC Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Young & Thompson
- Priority: JP2006-337489 20061214
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
In a semiconductor integrated circuit design method for carrying out a design of circuit patterns, a plurality of circuit patterns are defined, and each of the circuit patterns is composed of at least one minimum unit area. One of the circuit patterns is selected, and an expansion area is defined with respect to the selected circuit pattern so that the selected circuit pattern is at least included in the expansion area. An area ratio of an area size of the circuit pattern or circuit patterns included in the expansion area to an area size of the expansion area is calculated, and the area ratio is compared with a reference value.
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